FSTL Implementation

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🚧 This document is still being actively worked on and is subject to change. 🚧

Responsible	Naoki Sean Pross
Last Updated	10/12/2025, 12:48:54 PM
Last Author	Kai Berszin

Overview

• Altium Project

Logic Analyzer

The FSTL's main logic elements are two Raspbery Pi (RPI) Pico ICs, specifically the RP2354B variants because they have more GPIO pins.

This section is not complete

Power Rails

The FSTL can indvidually control 9 power rails. For each it can also measure the current.

Rails Control

The power rails are driven by high-side relays and are rated for 30V and 5A. The relays are themselves are driven by MOSFETs which can be controlled with 3.3V logic from the RPI.

Current Sensing

The sensing on each power rails is done through high side 50 mOhm shunt resistors, followed by a 20 V/V analog amplification and finally to a 16 bit SAR ADC. The shunt resistors are chosen such that we have 5A correspond to 5V after the amplification, therefore it must be rated for

$$R_s = \dfrac{ 5~\text{V} }{ 5~\text{A} \times 20 ~\text{V/V} } = 50 ~ \text{m}\Omega \implies P_s > 50 ~ \text{m}\Omega \times (5 ~ \text{A})^2 = 1.25 ~\text{W}.$$

The resulting precision is then

$$\dfrac{ 5 ~ \text{V} }{ 2^{16} ~ \text{bits} \times 20 ~ \text{V/V} \times 50 ~ \text{m}\Omega} = 76.3 ~ \mu \text{A / bit}.$$

The 16 channel ADC bank is made of two daisy-chained 8 channel ADCs and is is connected to the RPI via SPI. The SAR ADCs are not of the fastest type but they have a bandwidth of 500 kS/s. To read the data via SPI it requires $2 \times 16$ SCK falling edges, therefore to make use of the entire bandwidth the SPI clock speed required to keep a 500 kHz sampling rate is

$$f_\text{SCK} = 32 ~ \text{SCK} \times 500 ~ \text{kHz} = 16 ~ \text{MHz}.$$

Note that the ADS8688 has a maximum SPI clock speed of 17 MHz. For more details on the daisy-chained ADCs see Section "8.4.1.3.1 Daisy-Chain Topology" of the ADS8688 Datasheet.

USB Ports and Hub

The FSTL has an USB Type-C upstream connection and a 4 port USB hub connected downstream to the two RPIs on port 1 and 2. Ports 3 and 4 are connected to the USB-A connectors on the board. On the PCB the USB Hub IC has a indicator led which turns is the Hub is not configured correctly or has gone in suspend mode.

Upstream USB Type-C Port

The upstream port althogh USB Type-C only supports USB 2.0 (12 MBit/s), it is not used as power supply and and is electrically isolated on the D+ and D- lines. We do not want to draw power from the USB port of the computer connected to the FSTL.

Downstream USB Type-A Ports

Each downstream port can provide a maximum of 1A at 5V, and has overcurrent protection to prevent a faulty device from frying the FSTL (e.g. some cheap Aliexpress knockoffs adapters that may be used during testing). The ports are designed to work with full-speed USB 2.0 (12 MBit/s); High speed (480 MBit/s) may work but is not guaranteed.